Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor.pdf

Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor ˙ ´ Christopher LaFrieda Engin Ipek Jose F. Mart´ınez Rajit Manohar Computer Systems Laboratory Cornell University Ithaca, NY 14853 USA / Abstract presence of process variations, functional DMR pairs consisting of cores with different frequency or leakage characteristics may Aggressive CMOS scaling will make future chip multiproces- have to run at the speed of the slower core, leading to additional sors (CMPs) increasingly susceptible to transient faults, hard er- performance degradations. Hardwired DMR also presents limi- rors, manufacturing defects, and process variations. Existing tations to effective power density/thermal management, as DMR fault-tolerant CMP proposals that implement dual modular redun- pairs running code with similar power/thermal characteristics are dancy (DMR) do so by statically binding pairs of adjacent cores necessarily pl