ABSTRACT Analysis of Dynamic VoltageFrequency Scaling in ChipMultiprocessors.pdfVIP

Analysis of Dynamic Voltage/Frequency Scaling in Chip-Multiprocessors Sebastian Herbert Diana Marculescu Electrical and Computer Engineering Electrical and Computer Engineering Carnegie Mellon University Carnegie Mellon University 5000 Forbes Avenue 5000 Forbes Avenue Pittsburgh, PA 15213 Pittsburgh, PA 15213 sherbert@ dianam@ ABSTRACT increase in local power density and potentially linear scaling Fine-grained dynamic voltage/frequency scaling (DVFS) de- of performance for multithreaded workloads. CMPs are particularly well-suited to being implemented monstrates great promise for improving the energy-efficiency of chip-multiprocessors (CMPs), which have emerged as a as systems composed of multiple independently-clocked volt- popular way for designers to exploit growing transistor bud- age/frequency islands (VFIs). The division of a CMP into gets. We examine the tradeoffs involved in the choice of cores and shared cache provides a natural granularity for the both DVFS control scheme and method by which the pro- VFI partitioning, such that the performance cost of using cessor is partitioned into voltage/frequency islands (VFIs). the VFI organization is negligible. However, significant im- We simulate real multithreade