Design and Low Speed Testing of a FourBit RSFQ.pdfVIP

Design and Low Speed Testing of a Four-Bit RSFQ Multiplier-Accumulator † Quentin P. Herr, Nada Vukovic, Cesar A. Mancini, Kris Gaj, Qing Ke , Victor Adler, Eby G. Friedman, Andrzej Krasniewski††, Mark F. Bocko, and Marc J. Feldman Department of Electrical Engineering, University of Rochester, Rochester, NY 14627 †TRW Space Electronics Group, Redondo Beach, California ††Institute of Telecommunications, Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warszawa, Poland Abstract —We have designed and tested a four-bit RSFQ gates. Here we report successful low-speed operation; RSFQ multiplier-accumulator, the central component high-speed verification is currently in progress [3]. Due to its of our decimation digital filter. The circuit c o n s i s t s regular architecture, this four-bit MAC can be easily expanded of 38 synchronous RSFQ cells of six types arranged to an eight bit version, with the number of junctions scaling into a rectangular systolic array fed by one parallel proportionally with the number of bits. input and one serial input. Timing is based on a counter-flow clock distribution scheme with a In some ways, our multiplier accumulator is more complex simulated maximum clock frequency of 11 GHz. The than the main digital components of the two previously cited circuit, fabricated at Hypres, Inc., contains