Design, Impementation and Evaluation of an Explicit Rate Allocation Algorithm in an ATM Swi.pdfVIP

Design, Impementation and Evaluation of an Explicit Rate Allocation Algorithm in an ATM Switch Raman Muthukrishnan Lampros Kalampoukas K. K. Ramakrishnan Subhajit Dasgupta Bell Laboratories ATT Labs - Research Anujan Varma Holmdel, NJ 07733 Florham Park, NJ 07932 Computer Engineering Department University of California Santa Cruz, CA 95064 Abstract—We discuss a hardware implementation of an explicit rate al- bandwidth that can be allocated to each connection. Many such location algorithm for support of Available Bit Rate (ABR) service in ATM algorithms have been reported in the recent literature [2], [3], switches. We then demonstrate the effectiveness of the algorithm at the network-level through measurements on the actual implementation in a net- [4], [5], [6], [7], [8] (for a survey, see [9]). These, in general, can work testbed. The rate allocation algorithm has several desirable proper- be divided into algorithms that maintain per-VC bandwidth allo- ties, such as exact computation of the max-min rates, (1) computations cations, and those that do not. A state-maintaining algorithm, in per RM cell received, and ability to provide minimum cell rate (MCR) principle, has several advantages such as providing exact com- guarantees. We show that the algorithm can be implemented with a mod- est amount of hardware (64,000 gates in an Altera 10K100 programmable putation of max-min fair rates, ability