Industrial Evaluation of DRAM Tests.pdfVIP

Industrial Evaluation of DRAM Tests Ad J. van de Goor J. de Neef Delft University of Technology, Faculty of Information Technology and Systems Department of Electrical Engineering, Section Computer Architecture and Digital Technique Mekelweg 4, 2628 CD Delft, The Netherlands E-mail: A.J.vdGoor@its.tudelft.nl Abstract chips [1]. A test consists of a base test (BT) applied us- ing a particular stress combination (SC). An SC consists This paper presents the results of 44 well known mem- of a combination of values for the different stresses; e.g.; ory tests applied to 1896 1M*4 DRAM chips, using up to , Temp , etc. BTs have been per- 96 different stress combinations with each test. The results formed with up to 96 different SCs. show the importance of selecting the right stress combina- The organization of the paper is as follows: Section 2 tion, and that the theoretically better tests (i.e. those cov- gives an overview of the used BTs and stresses, Section 3 ering more different functional faults) also have a higher describes the results of the tests, while Section 4 ends with fault coverage. However, the currently used fault models conclusions. still leave much to be explained; e.g., the used data back- grounds and address orders show an unexplainable large 2. Used base tests and stresses variation