Logic Design of a Fast Circuit for Iterative Additions in Redundant Hybrid Number Systems.pdfVIP

Logic Design of a Fast Circuit for Iterative Additions in Redundant Hybrid Number Systems GIUSEPPE ALIA 1 AND ENRICO MARTINELLI2 1Dipartimento di Ingegneria dell’Informazione, Universit`a di Pisa, Via Diotisalvi, 2, 56126 Pisa, Italy 2Dipartimento di Ingegneria dell’Informazione, Universit`a di Siena, Via Roma, 56, 53100 Siena, Italy Email: alia@iet.unipi.it Repeated modular additions and overflow detection are possible in redundant hybrid number systems (RHNS). In this paper a circuit is proposed that implements the overflow-detecting procedure in such systems and allows a mean addition time of about 10.5 gate delays for numbers having a magnitude order normally distributed in the range [−233, 233 − 1], versus a 14 gate delay required by 32-bit CLA adders. Received November 27, 1995; revised December 11, 1997 1. INTRODUCTION distributed with the maximum value of probability selected in the range from 3 10−2 to 1128 8 10−3 (uniform Over the last two decades, considerable attention has distribution). been paid to residue number systems (RNSs) because of their fast, parallel arithmetic capabilities [1, 2, 3, 4, 5]. 2. HYBRID NUMBER SYSTEMS However, the major disadvantage of residue arithmetic, i.e. the absence of explicit information on number magnitude, The choice of a number system is es