基于VHDL的SPWM程序.docVIP

Ck 模块为降频（1:3） fenpin模块： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fenpint IS port(clk:in std_logic; addout:out std_logic_vector(9 downto 0)); end fenpint; architecture one of fenpint is signal addr :std_logic_vector(9 downto 0); begin process(clk) begin if clkevent and clk=1 then addr=addr+8; end if; end process; process(clk) begin if clkevent and clk=1 then addout=addr; end if; end process; end one; Fenpint 模块： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fenpint IS port(clk:in std_logic; addout:out std_logic_vector(9 downto 0)); end fenpint; architecture one of fenpint is signal addr :std_logic_vector(9 downto 0); begin process(clk) begin if clkevent and clk=1 then addr=addr+8; end if; end process; process(clk) begin if clkevent and clk=1 then addout=addr; end if; end process; end one; Compte 模块 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY compte IS PORT(clk:in std_logic; A:IN STD_LOGIC_VECTOR(7 DOWNTO 0); B:IN STD_LOGIC_VECTOR(7 DOWNTO 0); Y: OUT STD_LOGIC); END compte; ARCHITECTURE behave OF compte IS BEGIN PROCESS (A,B,clk) BEGIN if clkevent and clk=1 then IF (A = B) THEN Y =1; ELSE Y =0; END IF; end if; END PROCESS; END behave; 三角载波和正弦波的值可用波形文件产生 然后用分别添加到rom中 正弦波某个点的值和三角波128个点的值比较，当正弦波的点值大于三角波的点值，则spwm输出1，否则输出零。 Spwm输出接一个RC滤波器就可以输出比较漂亮的正弦波了（降低频率可提高幅度，当然最高只能3.3V，因为FPGA引脚输出的高电平为3.3V）