多核处理机系统Cache管理技术研究现状.pdfVIP

CN431258/ T P 2010 32 7 ISSN 1007130X COMPUT ER ENGINEERING SCIENCE Vol32, No7, 20 10 : 1007130X ( 20 10) * C che Rese rch Development of the Chip M ultiProcessor C che M n gement , SUO Guang, YANG Xuejun ( , 410073) ( School of Compute Science, National Unive sity of Defense Technology, Changsha 410073, China) : 多核处理器的 C che 结构设计和管理是微处理器设计领域的重要问题当前主流的商用微处理器均采用共 享最 一级C che 的系统结构, 而片上最 一级C che 的性能通常对处理器的性能影响较大, 因此共享C che 的管理问题 成为当前研究热点本文首先介绍当前主流多核处理器及其设计问题, 然 介绍了共享C che 管理的三项重要技术: 线程 调度NUCA 和C che 划分, 最 给出多核处理器C che 管理技术的发展方向 Abst act: It is import nt to design nd m n ge the c che resources in chip mult i processor. Currently, m instre m com merci l CPU s sh re their l st level c che w hile the perform nce of the l st level c ches h s gre t imp ct on the CPU per form nce. Therefore, sh red c che m n gement becomes n ctive rese rch re . In this p per , firstly, w e int roduce the design ch llenge of the CM P c che design nd the processors from the m instre m vendors. Secondly , w e put forw rd three key technologies of sh red c che m n gement: thre d scheduling , NUCA nd c che p rtitioning . Fin lly, w e conclude our p per nd point out the fut ure trend of the CMP c che design nd m n gement. : 多核处理器; 共享C che; 线程调度; NUCA ; C che 划分 Key wo ds: chip multiprocessor; sh red c che; thre d scheduling; NUCA ; c che p rtitioning doi: 10. 3969/ j. issn. 1007130X. 20 10. 07. 0 18 : T P302 : A , IBM[ 1] Intel[ 2] Sun[3] , 1 1 1 ,