Statistical PerformanceDriven Module Binding in HighLevel Synthesis.pdfVIP

Statistical Performance-Driven Module Binding in High-Level Synthesis Hiroyuki Tomiyama Akihiko Inoue Hiroto Yasuura Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University 6–1 Kasuga-koen, Kasuga, 816-8580 Japan Abstract or high-level synthesis techniques considering the variation of delay. Jyu and Malik proposed statistical timing opti- The inevitable fluctuation in fabrication processes re- mization methods for logic-level combinational circuits [3]. sults in LSI chips with various critical path delay even The methods maximize the percentage of fabricated circuits though all the chips are fabricated from the same design. which will achieve a certain performance level, given prob- Therefore, in LSI design, it is important to estimate what ability distributions of gate and wire delays. Tongsima et percentage of the fabricated chips will achieve the perfor- al. proposed a retiming technique, called probabilistic re- mance level and to maximize the percentage. This paper timing [10]. The probabilistic retiming minimizes the clock presents a model and a method to analyze statistical de- period of RT-level circuits, given probability distributions lay of RT-level datapath designs. The method predicts the of functional unit delays and a constraint on the percentage probability that the fabricated circuits will work at a user of fabricated circuits which will work at