《High Performance Interconnect Network for Tianhe System》.pdfVIP

Liao XK, Pang ZB, Wang KF High performance interconnect network for Tianhe system. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 30(2): 259–272 Mar. 2015. DOI 10.1007/s11390-015-1520-7 Xiang-Ke Liao (廖湘科), , Zheng-Bin Pang (庞征斌), Ke-Fei Wang (王克非), Yu-Tong Lu (卢宇彤), , Min Xie (谢 旻), Jun Xia (夏 军) De-Zun Dong (董德尊), and Guang Suo (所 光) E-mail: xkliao, zhengbinpang, kefeiwang, ytlu, xiemin, xiajun, dong, suoguang@ Received November 30, 2014; revised January 15, 2015. In this paper, we present the Tianhe-2 interconnect network and message passing services. We describe the architecture of the router and network interface chips, and highlight a set of hardware and software features effectively supporting high performance communications, ranging over remote direct memory access, collective optimization, hardware- enable reliable end-to-end communication, user-level message passing services, etc. Measured hardware performance results are also presented. Tianhe-2 supercomputer, interconnect network, router architecture, network interface architecture, user-level message passing 1 Introduction prove computing efficiency in post petaflops era, and plans to deliver a supercomputer achieving theoretical The Tianhe-2 (TH-2 or Milkyway-2) system, the peak performance of 100 petaflops by 2015. second generation of massively parallel supercompu- Tianhe-2, like its predecessor, Tianhe-1A, still em- ters in the TH series designed by National University ploys accelerator-based architectures. Each compute of Defense Technology (NUDT), was crowned as the node is equipped with two Intel Xeon E