An efficient memory allocation algorithm and hardware design with VHDL synthesis.pdfVIP

International Journal of Electronics, Vol. 95, No. 2, February 2008, 125–138 An efficient memory allocation algorithm and hardware design with VHDL synthesis F. KARABIBER*y, A. SERTBASy, S. OZDEMIRz and H. CAM‰ yComputer Engineering Department, Istanbul University, 34320, Avc|lar, Istanbul zComputer Engineering Department, Gazi University, 06570, Maltepe, Ankara ‰Computer Science and Engineering Department, Arizona State University Tempe, AZ 85287 (Received 27 November 2006; in final form 21 November 2007) This paper presents a hardware-efficient memory allocation technique, called EMA, that detects the existence of any free block of requested size in memory. EMA can allocate a free memory block of any number of chunks in any part of memory without having any internal fragmentation. The gate-level design of the hardware unit, along with its area-time measurements is given in this paper. Simulation results indicate that EMA is fast and flexible enough to allocate/deallocate a free block in any part of memory resulting in efficient utilization of memory spaces. In addition, the VHDL synthesis with FPGA implementation shows that EMA has less complicated hardware, and is faster than the known hardware techniques. Keywords: Memory allocation; Buddy system; Digital system design; VHDL synthesis; Simulation; FPGA 1. Introduction The high performance algorithms for dynamic memory allocation (DMA) have been of considerable interest in the literature as DMA is a critical factor for improving a computer system’s performance. The common allocation techniques can be divided into four categories: sequential fits, segregated fits, buddy system and bitmapped fit