《Design and Implementation of Three-Level》.pdf

2234 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007 Design and Implementation of Three-Level Space Vector PWM IP Core for FPGAs Haibing Hu, Wenxi Yao, and Zhengyu Lu, Senior Member, IEEE Abstract— This paper presents a novel circuit realization of balancing. Due to its complexity in computation, three-level the three-level space-vector pulse-width modulation (SVPWM) SVPWM algorithm is almost implemented using software based strategy. A simplified algorithm for the three-level SVPWM is on DSP or MCU according to reported literatures [5]–[11]. This proposed. Due to the geometrical symmetry of six sectors, there method demonstrates high flexibility and adaptability to various exist the close relationships in on time calculations and on time arrangement for switches between them. So it can complete the applications, but it also suffers some disadvantages: 1) As a se- computation of the three-level SVPWM in one sector. Conse- quence controller, these type processors interpret instructions quently, compared with the conventional algorithm, the proposed line by line, which results in time delay and leads to deteriorate algorithm is more suitable to hardware implementation by greatly the performance of a control system. 2) With most computa- reducing computation amount. Based on the simplified algorithm, tion resources devoting to the periodic events such as sampling, a three-level SVPWM intellectual property (IP) core has been control algorithm calculating and PWM gating signals gener- developed using