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《Electronic System-Level Synthesis Methodologies》.pdf
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1
Electronic System-Level Synthesis Methodologies
Andreas Gerstlauer, Member, IEEE, Christian Haubelt, Member, IEEE, Andy D. Pimentel, Senior Member, IEEE,
¨
Todor Stefanov, Member, IEEE, Daniel D. Gajski, Fellow, IEEE, and Jurgen Teich, Senior Member, IEEE
Abstract—With ever increasing system complexities, all major input of the synthesis flow. Such well-defined, rich input
semiconductor roadmaps have identified the need for moving to models are a prerequisite for later analysis and optimization.
higher levels of abstraction in order to increase productivity in Typical computational models in digital system design are
electronic system design. Most recently, many approaches and
tools that claim to realize and support a design process at the process networks, dataflow models or state machines. On the
so called Electronic System Level (ESL) have emerged. However, other hand, implementation platforms for such systems are
faced with the vast complexity challenges, in most cases at best often heterogeneous or homogeneous Multi-Processor System-
only partial solutions are available. on-Chip (MPSoC) solutions [4]. The complexity introduced
In this paper, we develop and propose a novel classification for by both, input computational model and target implementa-
ESL synthesis tools, and we will present six different academic
approaches in this context. Based on these observations, we can tion platform, results in a complex synthesis ste
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