《DATASHEET MC100EL35》.pdf

MC10EL35, MC100EL35 5VECL JK Flip-Flop Description The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH. The 100 Series contains temperature compensation. MARKING DIAGRAMS* Features • 525 ps Propagation Delay 8 8 8 1 • 2.2G Hz Toggle Frequency HEL35 KEL35 ALYW ALYW • ESD Protection: 1 kV Human Body Model, SOIC−8 100 V Machine Model D SUFFIX 1 1 CASE 751 • PECL Mode Operating Range: VCC = 4.2 V to 5.7 with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to 8 8 8 −5.7 V 1 HL35 KL35 • Internal Input Pulldown Resistors on J, K, CLK, and R ALYW ALYW • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test TSSOP−8