计算机组织与结构COA 12.pptVIP

* * * * * * * * * * * * * * * * * * Problem 16.2, indirect address Load Acc: fetch: indirect: execute: interrupt: Problem 16.5(a) Figure 10.14 (a) a. pop x free in use SP memory origin Problem 16.5(a) Figure 10.14 (a) a. pop x free in use SP memory origin free in use SP memory after pop Problem 16.5(b) Figure 10.14 (a) a. push x free in use SP memory origin free in use SP memory after push ISZ X Increment content and skip if zero t1: MAR ? (IRaddress) t2: MBR ? memory t3: MBR ? (MBR) + 1 t4: memory ? (MBR) if (MBR) == 0 then PC ? (PC) + 1 BSA X Branch and save address Address of instruction following BSA is saved in X Execution continues from X+1 t1: MAR ? (IRaddress) MBR ? (PC) t2: memory ? (MBR) PC ? (IRaddress) t3: PC ? (PC) + 1 M E M O R Y CR CW Table 16.1 MBR ? memory 16.5 Micro-operations ,C0 Subcycles micro-operations of ,C0 ,C0 ,C4 Table 16.1 micro-operation and control signals ? M E M O R Y Problem 16.2: control signals? CR CW 16.5 Example? Example? 16.4 Functions of Control Unit Sequencing Causing the CPU to step through a series of micro-operations Execution Causing the performance of each micro-op produce control signals Instruction Cycle Code (ICC) Subcycle Code 00: Fetch 01: Indirect 10: Execute 11: Interrupt The Instruction Cycle ICC Instruction Cycle Code Subcycle Code Int (from system bus) Ind (from IR) ICC ICC1 ICC0 Ind Int ICC1n+1 ICC0n+1 ICC clock Ind,Int: valid=high Elements of Program Execution a=(x+y)*(z+w) ADD R1,X substep smaller cycle shorter subcycle Micro-operation t1 t2 t3 00 11 10 01 Micro-operations ICC=00 ICC=01 ICC=11 ,C0 Subcycles micro-operations of ,C0 ,C0 ,C4 Opcode Address Decoder LOAD STORE ADD AND JUMP JUMPc CMPL IR Opcode I1,I2,I3 I0 Ind 0 5 4 3 2 1 6 I0,I1,I2,I3 ICC Ind Int Opcode ACC=0 16.10 Problems With Hardwired Designs Complex logic Difficult to design and test Inflexible design To produce control signals Hardwire