DrawbacksofMetal-gateMOSTransistors.ppt

EE 4345Semiconductor Electronics Design Project CMOS Process Mohammad Butt Ahmad Elmardini Devices Heithem Souissi Dina Miqdadi Process Extension Fares Alnajjar Wyatt Sullivan CMOS Process Drawbacks of Metal-gate MOS Transistors Metal-gate PMOS transistors cannot maintain the minimal(+0.5V) threshold variation. Excess surface state charges and mobile ion contamination are two main sources of threshold variation. Suffer from excessive overlap capacitance. Parasitic capacitances Cgs and Cgd slow the transistor because they must be charged and discharged during switching. Aluminum is used as gate material which can erode completely causing contact spiking. Features of Polysilicon-gate CMOS Process Consists of nine masking steps Optimized to form complementary PMOS and NMOS transistors on a common substrate Can also fabricate some analog circuits with slight modifications Use (100) silicon to reduce surface state density and improve threshold voltage control Polysilicon-gate is doped with phosphorus to minimize mobile ion contamination, resulting in faster switching speeds and better control of threshold voltage Oveview of Polysilicon-gate CMOS Process Start with P-substrate Grow P-type epitaxial layer on the substrate Create N-well regions and channel stop regions Grow gate oxide (thin oxide) and field oxide (thick oxide) Deposit and pattern polysilicon layer Implant source and drain regions, substrate contacts Create contact windows, deposit and pattern metal layer Epitaxial Growth P-type substrate is doped with as much boron as possible to minimize substrate resistivity Lightly doped P-type epitaxial layer is grown on substrate NMOS transistors are formed directly on the epi layer which serves as a backgate N-well Diffusion The wafer is then oxidized and etched to open windows through which ion implantation deposits a controlled dose of phosphorus A prolonged drive creates a deep lightly doped N-type region called N-well Thermal oxidation covers the exposed sil