TheDigitalLogicLevel.pptVIP

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0 The Digital Logic Level Chapter 3 Gates and Boolean Algebra (1) (a) A transistor inverter. (b) A NAND gate. (c) A NOR gate. Gates and Boolean Algebra (2) The symbols and functional behavior for the five basic gates. Boolean Algebra (a) Truth table for majority function of three variables. (b) A circuit for (a). Circuit Equivalence (1) Construction of (a) NOT, (b) AND, and (c) OR gates using only NAND gates or only NOR gates. Circuit Equivalence (2) Two equivalent functions (a) AB + AC, (b) A(B + C). Circuit Equivalence (3) Some identities of Boolean algebra. Circuit Equivalence (4) Alternative symbols for some gates:(a) NAND, (b) NOR, (c) AND, (d) OR Circuit Equivalence (5) (a) The truth table for the XOR function. (b-d) Three circuits for computing it. Circuit Equivalence (6) (a) Electrical characteristics of a device. (b) Positive logic. (c) Negative logic. Integrated Circuits An SSI chip containing four gates. Multiplexers (1) An eight-input multiplexer circuit. Multiplexers (2) (a) An MSI multiplexer. (b) The same multiplexer wired to compute the majority function. Decoders A 3-to-8 decoder circuit. Comparators A simple 4-bit comparator. Programmable Logic Arrays A 12-input, 6-output programmable logic array. The little squares represent fuses that can be burned out. Shifters A 1-bit left/right shifter. Adders (1) (a) A truth table for 1-bit addition. (b) A circuit for a half adder. Adders (2) (a) Truth table for a full adder. (b) Circuit for a full adder. Arithmetic Logic Units (1) A 1-bit ALU. Arithmetic Logic Units (2) Eight 1-bit ALU slices connected to make an 8-bit ALU. The enables and invert signals are not shown for simplicity. Clocks (a) A clock. (b) The timing diagram for the clock. (c) Generation of an asymmetric clock. Latches (1) (a) NOR latch in state 0. (b) NOR latch in state 1. (c) Truth table for NOR.