ee3.cma-ComputerArchitecture-UniversityofSurrey.ppt

* EE3.cma - Computer Architecture * The T3D Network After simulation the T3D network was chosen to be a 3D torus (as is the T3E) Note: config. max latency average latency 8-node ring 4 hops 2 hops 2D, 4*2 torus 3 hops 1.5 hops 3D, 2*2*2 torus 2 hops 1 hop The Cray T3D 2D torus 4*4 cube = 4*2 2D torus hyper-cube * EE3.cma - Computer Architecture * T3D Macro-architecture The T3D designers have decided that the programmer’s view of the architecture should include: globally-addressed physically-distributed memory characteristics visible topological relationships between PEs synchronisation features visible from a high level Their goal is led by the need to provide a slowly-changing view (to the programmer) from one hardware generation to the next. T3D Micro-architecture Rather than choosing to develop their own processor, Cray selected the DEC Alpha processor: 0.75 mm CMOS RISC processor core 64 bit bus 150MHz, 150 MFLOPS, 300MIPS (3 instructions/cycle) 32 integer and 32 FP registers 8Kbytes instruction and 8Kbytes data caches 43 bit virtual address space The Cray T3D * EE3.cma - Computer Architecture * Latency Hiding The DEC Alpha has a FETCH instruction which allows memory to be loaded into the cache before it is required in an algorithm. This runs asynchronously with the processor 16 FETCHes may be in progress at once - they are FIFO queued When data is received, it is slotted into the FIFO, ready for access by the processor The processor stalls if data is not available at the head of the FIFO when needed Stores do not have a a latency - they can proceed independently of the processor (data dependencies permitting) Synchronisation Barrier Synchronisation no process may advance beyond the barrier until all processes have arrived used as a break between 2 blocks of code with data dependencies supported in hardware - 16 special registers - bits set to 1 on barrier creation; set to 0 by arriving process; hardware interrupt on completion Messaging (a form of s