Lecture13-AuburnUniversity.pptVIP

Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 13 ELEC 5270/6270 Fall 2007Low-Power Design of Electronic Circuits Pseudo-nMOS, Dynamic CMOSand Domino CMOS Logic Why Not Static CMOS? Advantages: Static (robust) operation, low power, scalable with technology. Disadvantages: Large size: An N input gate requires 2N transistors. Large capacitance: Each fanout must drive two devices. Alternatives: Pass-transistor logic (PTL), pseudo-nMOS, dynamic CMOS, domino CMOS. A Pseudo-nMOS Gate Pseudo-nMOS NOR Pseudo-nMOS NAND Pseudo-nMOS Inverter Inverter Characteristics Performance of Inverter Negative Aspects of Pseudo-nMOS Output 0 state is ratioed logic. Faster gates mean higher static power. Low static power means slow gates. A Dynamic CMOS Gate Two-Phase Operation in a Vector Period 4-Input NAND Dynamic CMOS Gate Characteristics of Dynamic CMOS Nonratioed logic – sizing of pMOS transistor is not important for output levels. Smaller number of transistors, N+2 vs. 2N. Larger precharge transistor reduces output fall time, but increases precharge power. Faster switching due to smaller capacitance. Static power – negligible. Short-circuit power – none. Dynamic power no glitches – following precharge, signals can either make transitions only in one direction, 1→0, or no transition, 1→1. only logic transitions – all nodes at logic 0 are charged to VDD during precharge phase. Switching Speed and Power Fewer transistors mean smaller node capacitance. No short-circuit current to slow down discharging of capacitance. Only dynamic power consumed, but can be higher than CMOS. Logic Activity Probability of 0 → 1 transition: Static CMOS, p0 p1 = p0(1 – p0) Dynamic CMOS, p0 ≥ p0 p1 Example: 2-input NOR gate Static CMOS, Pdyn = 0.1875 CLVDD2fCK Dynamic CMOS, Pdyn = 0.75 CLVDD2fCK Charge Leakage Bleeder Transistor A Problems With Dynamic CMOS Remedy Set all inputs to gates to 0 during precharge. Since precharge raises all outputs to 1, inserting inverters between gates will do the tric