VHDL时序电路设计..ppt

S0 S2 0/0 1/0 S3 1/0 S1 1/1 0/0 0/1 0/0 1/0 输出信号和输入信号无关。 输入信号影响状态的转换。 ①More型状态机 S0 S2 0/0 1/0 S3 1/1 S1 1/1 0/0 0/0 0/0 1/1 ②Mealy型状态机 Mealy型状态机示例—序列信号检测器 序列信号：110 序列检测器 CLK Z x S0 S2 0/0 1/0 S1 1/0 0/1 0/0 1/0 序列信号检测器—状态图 序列信号：110 S x/Z ‘1’ ‘11’ LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY sqs IS PORT( x,clk: in Std_logic; z: out Std_logic); END sqs; ARCHITECTURE a OF mealy IS TYPE STATE_TYPE IS (s0, s1, s2); SIGNAL state: STATE_TYPE; BEGIN PROCESS (clk) BEGIN If （clk’EVENT AND clk = ‘1’） then CASE state IS WHEN