Product ObsoleteUnder Obsolescence APPLICATION NOTE.pdfVIP

Product Obsolete/Under Obsolescence APPLICATION NOTE Efficient Shift Registers, LFSR  Counters, and Long Pseudo- Random Sequence Generators XAPP 052 July 7,1996 (Version 1.1) Application Note by Peter Alfke Summary Shift registers longer than eight bits can be implemented most efficiently in XC4000E Select-RAMTM . Using Linear Feedback Shift-Register (LFSR) counters to address the RAM makes the design even simpler. This application note describes 4- and 5-bit universal LFSR counters, very efficient RAM-based 32-bit and 100-bit shift registers, and pseudo-random sequence generators with repetition rates of thousands and even trillions of years, useful for testing and encryption purposes. The appropriate taps for maximum-length LFSR counters of up to 168 bits are listed. Xilinx Family Demonstrates XC4000E, XC4000L, XC4000EX, XC4000XL Shift registers implemented in RAM LFSR counters Introduction The XC4000E on-chip distributed synchronous RAM archi- the feedback for those states, the 4-bit LFSR counter tecture lends itself well to the efficient implementation of counts modulo 16, and has no lock-up state. Counters with long shift registers. The 16 x 1 or 32 x 1 RAM behaves like a shorter cycle require additional decoding of the feedback an edge-triggered register. An address counter supplies signal, as shown in Table 1 and Figure 1. Any such decod- sequential addresses, but there is no need for a conven- ing is easi