Custom Code Generation for Soft Processors - University of.pptVIP

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Custom Code Generation for Soft Processors - University of.ppt

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Custom Code Generation for Soft Processors - University of.ppt

Custom Code Generationfor Soft Processors Soft Processor: Processor in FPGA Application-Specific Code Generation Infrastructure SPREE System (Soft Processor Rapid Exploration Environment) Back-End Infrastructure Area efficiency A combined metric: Representative Processors SPREE vs Nios II Code Generation Options Studied( Outline ) Low-level hardware-software tradeoffs Reducing hardware shift support Removing hazard detection logic Impact of unique ISA features Removing delay slots Hi/Lo registers vs 3-operand multiplies Using unaligned memory load and stores Application-specific register management Operand scheduling and forwarding lines Limiting the use of architected registers Combining these into app-specific optimizations Reducing Hardware Shift Support Best performance per area: Using hard multiplier for shifting Multiplications and shifts: both in software? Software shifting using additions subtractions Impact of removing the dedicated LUT-based shifter? Costs ~250LEs, 30% of smallest soft processor Can we have partial hardware support for shifting? Area for Various Shift Strategies (Pipe3) Dynamic Instructions Containing Shifts How to get rid of the shifter Software-only shifts require an order of magnitude more cycles to compute Measure the cost in cycles for each shift operation Replace shifts by hard shifts and/or software shifts: Impact of up to 2 Fixed-Amount Shifters (pipe3) Removing Delay Slots Default MIPS has branch and load delay slots Under what conditions are they worth it? Load delay slots need no additional hardware support Because of hazard detection in the processor Branch delay slots require hardware support We only have predict-not-taken so far Are working on better branch prediction Removing Load Delay Slots (serial) Removing Branch Delay Slots 3-Operand Multiplies vs Hi/Lo Registers Default MIPS has Hi/Lo registers Motivated by multi-cycle multiplies Hold multiplication results (Hi and Lo each 32 bits) Two special instructions to acc