Dynamic Verification of Sequential Consistency.pptVIP

Dynamic Verification of Sequential Consistency Introduction Multithreaded systems becoming ubiquitous Commercial workloads rely heavily on parallel machines Reliability and availability are crucial Backward Error Recovery can provide high availability Recover to known good state upon error But can only recover from errors detected in time Memory system is of special interest Complex – Many components, large transistor count Numerous error hazards Memory System Error Detection Must cover all memory system components DRAMs, caches, controllers, interconnect, and write buffers Mechanisms for individual components exist Storage structures: ECC Interconnect: checksums, sequence numbering Cache and memory controllers: replication Adding detection to all components is hard Complicates design of every component Requires good intuition of interactions and possible errors ? Want comprehensive, end-to-end error detection Dynamic Verification Dynamic verification Correct system operation constantly monitored at runtime End-to-end scheme Detects transient errors, design bugs, and manufacturing errors Differs from statically verifying that design is bug-free High level invariants are checked, instead of individual components Simplified design of system components Can detect any low-level error that violates invariant Memory Consistency Memory consistency model Formal specification of memory system behavior in a multithreaded system Defines order in which memory accesses from different CPUs can become globally visible Many consistency models exist, we focus on one Verifying memory consistency =Verifying correctness of the memory system Ideal invariant for dynamic verification Sequential Consistency (SC) Requires appearance of total global order of all loads and stores in system Each load must receive value of most recent store in total order to the same address Program order of all processors is preserved in total order SC is most intuitive consistency model Good for pro