用vhdl设计数字秒表.docVIP

实验五 数字秒表的设计 1、分频计的设计 （1）分频计的源程序代码 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FP IS PORT(CLK: IN STD_LOGIC; NEWCLK: OUT STD_LOGIC); END FP; ARCHITECTURE ART OF FP IS SIGNAL CNTER: INTEGER RANGE 0 TO 10#29999#; BEGIN PROCESS(CLK) IS BEGIN IF CLKEVENT AND CLK=1 THEN IF CNTER=10#29999# THEN CNTER=0; ELSE CNTER=CNTER + 1; END IF; END IF; END PROCESS; PROCESS(CNTER) IS BEGIN IF CNTER=10#29999# THEN NEWCLK=1; ELSE NEWCLK=0; END IF; END PROCESS; END ART; （2）分频计的封装图 2、六进制计数器的设计 （1）六进制计数器的源程序代码 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY TN6 IS PORT(CLK: IN STD_LOGIC; CLR: IN STD_LOGIC; ENA: IN STD_LOGIC; CQ: OUT INTEGER RANGE 0 TO 15; CARRY_OUT: OUT STD_LOGIC); END TN6; ARCHITECTURE ART OF TN6 IS SIGNAL CQI: INTEGER RANGE 0 TO 15; BEGIN PROCESS(CLK,CLR,ENA) IS BEGIN IF CLR=1 THEN CQI=0; ELSIF CLKEVENT AND CLK=1 THEN IF ENA=1 THEN IF CQI5 THEN CQI=CQI+1; ELSE CQI=0;END IF; END IF; END IF; END PROCESS; PROCESS(CQI) IS BEGIN IF CQI=5 THEN CARRY_OUT=1; ELSE CARRY_OUT=0; END IF; END PROCESS; CQ=CQI; END ART; （2）六进制的封装图 3、十进制计数器的设计 （1）十进制计数器源程序代码 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY TN10 IS PORT(CLK: IN STD_LOGIC; CLR: IN STD_LOGIC; ENA: IN STD_LOGIC; CQ: OUT INTEGER RANGE 0 TO 15; CARRY_OUT: OUT STD_LOGIC); END TN10; ARCHITECTURE ART OF TN10 IS SIGNAL CQI: INTEGER RANGE 0 TO 15; BEGIN PROCESS(CLK,CLR,ENA) IS BEGIN IF CLR=1 THEN CQI=0; ELSIF CLKEVENT AND CLK=1 THEN IF ENA=1 THEN IF CQI9 THEN CQI=CQI+1; ELSE CQI=0;END IF; END IF; END IF; END PROCESS; PROCESS(CQI) IS BEGIN IF CQI=9 THEN CARRY_OUT=1; ELSE CARRY_OUT=0; END IF; END PROCESS; CQ=CQI; END ART; （2）十进制计数器的封装图 4、扫描电路的设计 （1）扫描电路的源程序代码 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SCAN IS PORT(scanclk:in std_logic; count1,Count2,count3,count4,count5,count6:in std_logic_VECTOR(3 DOWNTO 0); S:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END ENTITY SCAN; ARCHITEC