电子科技大学2012年数电半期考试题参考解答.docVIP

电子科技大学二零壹壹年至二零一贰学年第二学期 “数字逻辑设计及应用”课程考试题（半期）（120分钟） 考试日期 2012年4月22日 一 二 三 四 五 六 七 八 九 十 总分 评卷教师 I. To fill the answers in the “( )” (2’ X 20=40) 1. [42.25 ]10 = ( 2A.4 )16 = ( 52.2 )8 . 2. The binary two’s complement is （1011）, then its corresponding 8-bit two’s complement is ( ), and 8-bit one’s complement is (), and 8-bit signed-magnitude is (). 3. The 8421-BCD code is8421-BCD，then its corresponding decimal number is ( 98 ). 4. The binary number code is 2, then its corresponding Gray code is ( ). 5. If F = ∏ABC (1,3,5)，then its dual expression is ∑ABC ( 2,4,6 ), and the complement expression of the function F is F’=∑ABC ( 1,3,5)。 6. The range of 8-bit two’s complement is (-128 ~ 127), and the range of 8-bit unsigned binary number is (0 ~ 255). 7. If there are 2012 different states, we need at least ( 11 ) bits binary code to represent them. 8. For the two’s complement addition and subtraction operation, if [ A ] two’s-complement and [ B] two’s-complement, calculate [-A-B ] two’s-complement, [A-B ] two’s-complement , and indicate whether or not overflow occurs. [-A-B ] two’s-complement = [ ], overflow: [ yes ] [A-B ] two’s-complement = [ ], overflow: [ no ] 9. The maximum LOW-state output current IOLmax for an HC-series CMOS gate driving CMOS inputs is 0.02mA, the maximum HIGH-state output current IOHmax is -0.02mA, and the maximum input current IImax for an HC-series CMOS input in any states is , the DC fanout at HIGH-state is ( 20 ). 10. The unused CMOS NAND gate inputs should be tied to logic ( 1 ). 11. The following logic diagram Fig.1 implements a function of 3-variable with a 74x138. The logic function can be expressed as F (A,B,C) =∏A,B,C ( 2, 3,4,5,7 ). Fig.1 12. The CMOS circuit is shown in Fig.2. Write the function of the circuit. ( F=(AB+C+D)’ ) Fig.2 II.