基于VHDL语言的EDA实验报告.docVIP

E D A 实 验 报 告 班级：电科五班 姓名：张红义 学号: 1008101143 半加器 全加器 十进制计数器 实验源码： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS PORT (CLK,RST,EN,LOAD:IN STD_LOGIC; DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT:OUT STD_LOGIC ); END CNT10; ARCHITECTURE behav OF CNT10 IS BEGIN PROCESS(CLK,RST,EN,LOAD) VARIABLE Q:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF RST=0 THEN Q:=(OTHERS=0); ELSIF CLKEVENT AND CLK=1 THEN IF EN=1 THEN IF (LOAD=0) THEN Q:=DATA;ELSE IF Q9 THEN Q:=Q+1; ELSE Q:=(OTHERS=0); END IF; END IF; END IF; END IF; IF Q=1001 THEN COUT=1; ELSE COUT=0;END IF; DOUT=Q; END PROCESS; END behav; 仿真波形： 封装图： 3-8译码器 实验源码： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY YM38 IS PORT (A:IN STD_LOGIC_VECTOR(2 DOWNTO 0); EN:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END YM38; ARCHITECTURE BEHAV OF YM38 IS SIGNAL CLK: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN CLK=AEN; PROCESS(CLK) BEGIN CASE CLK IS WHEN 0001 = Y WHEN 0011 = Y WHEN 0101 = Y WHEN 0111 = Y WHEN 1001 = Y WHEN 1011 = Y WHEN 1101 = Y WHEN 1111 = Y WHEN OTHERS= Y END CASE; END PROCESS; END BEHAV; 仿真波形： 封装图： MEALY型有限状态机 实验源码: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MEALY1 IS PORT(CLK,DIN1,DIN2,RST : IN STDD_LOGIC; Q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); END MEALY1; ARCHITECTURE BEHAV OF MEALY1 IS TYPE STATES IS (ST0, ST1, ST2, ST3,ST4); SIGNAL PST :STATES ; BEGIN REGCOM: PROCESS(CLK,RST,PST,DIN1) BEGIN IF RST=1 THEN PST =ST0; ELSIF RISING_EDGE(CLK) THEN CASE PST IS WHEN ST0= IF DIN1=1 THEN PST=ST1 ; ELSE PST=ST0 ; END IF ; WHEN ST1= IF DIN1=1 THEN PST=ST2 ; ELSE PST=ST1 ; END I