数字电路第六章要点解析.ppt

Chapter6  Combinational Logic Design Practices Chapter Outline Documentation Standards Digital Circuit Timing and Propagation delay Combinational Logic Design Structures :- Decoders - Encoders - Three-State Buffers- Multiplexers- EXCLUSIVE OR Gates and Parity Circuits- Comparators- Adders/ Subtractors- Arithmetic Logic Units ( ALUs) 6.1 Documentation Standard(文档标准) Documentation of a digital system should provide the necessary information for building, testing ,operating , and maintaining the system. Specification: Description of Interface and Function (说明书：接口及功能描述) Block Diagram: System’s Major Function Module and their Basic Interconnections (方框图 ：主要功能模块及其互联 P345图6-1) Schematic Diagram: showing all the components, their types, and all interconnections (原理图 （P360图6-17）) Documentation Standard(文档标准) Timing Diagram: showing the logic signals as a function of time (定时图 （P363图6-19）) Structure Logic Device Description: showing the operation of the structures (结构化逻辑器件描述) Circuit Description : Explains how the circuit works internally. (电路描述：解释电路内部如何工作) Gate Symbols (门的符号) DeMorgan equivalent symbols(等效门符号（摩根定理）) Signal Names and Active Levels (信号名和有效电平) Signal name: a descriptive alphanumeric label for each input/output signal. In real system, well-chosen names convey information to readers Each signal name should have an active-level associated with it. (有效电平) Active High （高电平有效） Active Low （低电平有效） Signal Name and Active Levels (信号名和有效电平) Signal Name and Active Levels (信号名和有效电平) Bubble-to-Bubble Logic Design(“圈到圈”的逻辑设计) Purpose : To make it easy to understand the function of the Logic circuit by choosing appropriate logic symbols and signal names including active-level designators. Bubble-to-Bubble Logic Design(“圈到圈”的逻辑设计) 6.2 Circuit Timing (电路定时) 6.2 Circuit Timing (电路定时) 6.2 Circuit Timing (电路定时) 6.2 Circuit Timing (电路定时) 6.2 Circuit Timing (电路定时) Commonly Used MSI Combinational Logic Device Decoders (译码器) En