电子设计自动化基础- 7综合基础知识.ppt

综合基本知识 李晓明 内容 模块综合过程 关键约束介绍 约束文件实例 DC图形界面 综合的过程 Synthesis Is Constraint-Driven 模块综合过程 工艺库 设计目标 设计目标 Setting Design Rule Constraints the most commonly specified design rule constraints: Transition time Fanout load Capacitance Setting Transition Time Constraints The transition time of a net is the time required for its driving pin to change logic values. Design Compiler calculates the transition time for each net by multiplying the drive resistance of the driving pin by the sum of the capacitive loads connected to the driving pin. Setting Fanout Load Constraints The maximum fanout load for a ne