Architecture and Routing for NoC-based FPGA.pptVIP

Architecture and Routing for NoC-based FPGA Israel Cidon* One NoC does not fit all! Field Programmable Gate Array - 101 Flexible Soft logic Configurable logic blocks (CLBs) and routing channels Programmed Look-up-tables (LUTs) Configurable switching boxes Area, power and speed efficient Hard logic Wire and clock infrastructure Special purpose modules, e.g., CPU, SerDes FPGA Example Challenges for Future FPGA Scalability of design methodology Dominance of wire delays Already more than 50% of delay Power Complex communication patterns Prototyping for NoC-based SoCs NoC Based FPGA Architecture Future FPGA: NoC-Based Hierarchical: Divide chip into regions Programmable wiring inside regions Regions interconnected by NoCs Scalable Short wires, spatial reuse, power cost Modular design Prototype for NoC based SoC Hard or soft NoC? Why hard Interconnect is a performance bottleneck Interconnect power Part of FPGA infrastructure Why soft Application is not known when the network is built Provides maximum flexibility Prevents resource lockup Suggested FPGA NoC Architecture FPGA Routing – Optimization Problem The NoC design problem The cost Hard grid links For uniform grids - the capacity of the most congestion link NoC Logic Hard logic for router Soft logic for routing tables, headers, CNIs Routing Schemes XY Very simple logic Deadlock free Unbalanced - high cost in uniform capacity grids Toggle XY (TXY) Split packets evenly between XY, YX routes Deadlock avoided with 2 VCs Near-optimal for symmetric traffic (permutations) [Seo et al. 05; Towles Dally 02] Simple Better Balanced Split routes Does not take into account the traffic pattern Weighted Schemes TXY not always produces the best results - WTXY Given a traffic pattern, choose XY/YX ratio of lowest maximum capacity Compute the ratio at programming time Load into Cxy field in router Router chooses XY route with probability Cxy, otherwise YX TXY, WTXY Limitation Traffic split packets of the same flow tak