COMP 206Computer Architecture and Implementation.pptVIP

COMP 206Computer Architecture and Implementation.ppt

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COMP 206Computer Architecture and Implementation.ppt

COMP 206: Computer Architecture and Implementation Montek Singh Mon, Oct 10, 2005 Topic: Instruction-Level Parallelism (Dynamic Scheduling: Tomasulo’s Algorithm) Reading Chapter 3: ILP and Its Dynamic Exploitation Section 3.1-3.3 Dynamic Scheduling: Tomasulo’s Algorithm For IBM 360/91 (about three years after CDC 6600) Goal: High performance without special compilers Differences between IBM 360 and CDC 6600 ISA IBM has only 2 register specifiers/instruction versus 3 in CDC 6600 IBM has 4 FP registers versus 8 in CDC 6600 Differences between Tomasulo Algorithm and Scoreboard Control and buffers distributed with Function Units versus centralized in scoreboard; called “reservation stations” Registers in instructions replaced by pointers to reservation station buffer Hardware renaming of registers to avoid WAR and WAW hazards Common Data Bus broadcasts results to all FUs (forwarding) Load and Stores treated as FUs as well Tomasulo: Organization More Details of Tomasulo Organization Entities that produce values are assigned 4-bit tags 1, 2, 3, 4, 5, 6 for load buffers 8, 9 for multiplier reservation stations 10, 11, 12 for adder reservation stations Tag 0 indicates presence of valid data FP registers have “busy bits” 0 means that register holds valid data 1 means that it is waiting to receive value from source identified by its tag field Tomasulo: Representing Data Dependences Inputs Operand is a register with busy bit = 0 Data copied immediately (through register bus) into reservation station Tag field of RS set to 0 Operand is a register with busy bit = 1 Tag field of RS receives a copy of the register tag field Operand is a load buffer that contains valid data Data copied into RS Operand is a load buffer that is awaiting data Tag field of RS receives tag of load buffer Outputs Output is a register Busy bit set to 1, tag set to RS tag Output is a store buffer Tag set to RS tag, destination address set Three Stages of Tomasulo Algorithm Issue: get instruction from

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