Future of Computer Architecture.pptVIP

Future of Computer Architecture David A. Patterson Pardee Professor of Computer Science, U.C. Berkeley President, Association for Computing Machinery High Level Message Everything is changing; Old conventional wisdom is out We DESPERATELY need a new architectural solution for microprocessors based on parallelism Need to create a “watering hole” to bring everyone together to quickly find that solution architects, language designers, application experts, numerical analysts, algorithm designers, programmers, … Outline Part I: A New Agenda for Computer Architecture Old Conventional Wisdom vs. New Conventional Wisdom Part II: A “Watering Hole” for Parallel Systems Research Accelerator for Multiple Processors Conclusion Conventional Wisdom (CW)  in Computer Architecture Old CW: Chips reliable internally, errors at pins New CW: ≤65 nm ? high soft hard error rates Old CW: Demonstrate new ideas by building chips New CW: Mask costs, ECAD costs, GHz clock rates ? researchers can’t build believable prototypes Old CW: Innovate via compiler optimizations + architecture New: Takes 10 years before new optimization at leading conference gets into production compilers Old: Hardware is hard to change, SW is flexible New: Hardware is flexible, SW is hard to change Conventional Wisdom (CW)  in Computer Architecture Old CW: Power is free, Transistors expensive New CW: “Power wall” Power expensive, Xtors free (Can put more on chip than can afford to turn on) Old: Multiplies are slow, Memory access is fast New: “Memory wall” Memory slow, multiplies fast (200 clocks to DRAM memory, 4 clocks for FP multiply) Old : Increasing Instruction Level Parallelism via compilers, innovation (Out-of-order, speculation, VLIW, …) New CW: “ILP wall” diminishing returns on more ILP New: Power Wall + Memory Wall + ILP Wall = Brick Wall Old CW: Uniprocessor performance 2X / 1.5 yrs New CW: Uniprocessor performance only 2X / 5 yrs? Uniprocessor Performance (SPECint) Sea Change in Chip Design Intel 4