Efficient VLSI Architectures of Split-Radix FFT using New Distributed Arithmetic.pdfVIP

International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-3, Issue-1, March 2013 Efficient VLSI Architectures of Split-Radix FFT using New Distributed Arithmetic Ansuman DiptiSankar Das, Abhishek Mankar, N Prasad, K. K. Mahapatra, Ayas Kanta Swain Abstract—Fast Fourier transform (FFT) has become One of the disadvantages of conventional FFT architectures ubiquitous in many engineering applications. Efficient is the presence of multiplier blocks, which has increased algorithms are being designed to improve the architecture of hardware, increased power consumption and reduced FFT. Among the different proposed algorithms, split-radix FFT operating frequency. The basic FFT design is based on has shown considerable improvement in terms of reducing radix-2 butterfly block, which was proposed by Cooley- hardware complexity of the architecture compared to radix-2 and radix-4 FFT algorithms. New distributed arithmetic (NEDA) is Tukey [7]. Recent advances in the algorithm include FFT one of the most used techniques in implementing multiplier-less architectures based on higher and split-radix such as radix-4, k architectures of many digital systems. This paper proposes radix-8, radix-2 , etc. [8] – [12]. efficient multiplier-less VLSI architectures of split-radix FFT Split-radix FFT is one of the