中科院_专用集成电路设计_作业3实用技术.docxVIP

PAGE \* MERGEFORMAT6 Assignment 3 Using HSPICE and TSMC 0.18 μm CMOS technology model with 1.8 V power supply, plot the subthreshold current IDSUB versus VBS, and the saturation current IDSAT versus VBS for an NMOS device with W=400 nm and L=200 nm. Specify the range for VBS as 0 to –2.0 V. Explain the results. 解： 亚阈值电流IDSUB, 其中VGS=VDS=0.3V b)饱和电流IDSAT, 其中VGS=2.0V, VDS=10V 图1 波形仿真 从上面两个图可以看出，随着|VBS| 的增大，ID在减小。究其原因，可能是当VBS增大时，空间电荷区感应出的电荷数目增大，这相当于耗尽层加宽，导电沟道变窄，阈值电压增加，VGS需要更大的能量来克服阈值电压达到导通，从而引起电流IDS减小。 两图的代码如下： 亚阈值电流IDSUB * SPICE INPUT FILE: Bsim3demo1.sp ID-VBS .param Supply=1.8 * Set value of Vdd .lib D:\Program Files (x86)\synopsys\Hspice_D-2010.03-SP1\mm018.l TT * Set 0.18um library .opt scale=0.1u * Set lambda *.model nch NMOS level=49 version=3.1 mn drainn gaten Gnd bodyn nch l=2 w=4 ad=20 pd=4 as=20 ps=4 Vdd Vdd 0 Supply Vgsn gaten 0 0.3 Vdsn drainn 0 0.3 Vbsn bodyn Gnd Supply .dc Vbsn 0 -2.0 -0.05 .print dc I1(mn) .end 饱和电流IDSAT * SPICE INPUT FILE: Bsim3demo2.sp ID-VBS .param Supply=1.8 * Set value of Vdd .lib D:\Program Files (x86)\synopsys\Hspice_D-2010.03-SP1\mm018.l TT * Set 0.18um library .opt scale=0.1u * Set lambda *.model nch NMOS level=49 version=3.1 mn drainn gaten Gnd bodyn nch l=2 w=4 ad=20 pd=4 as=20 ps=4 Vdd Vdd 0 Supply Vgsn gaten 0 2.0 Vdsn drainn 0 10.0 Vbsn bodyn Gnd Supply .dc Vbsn 0 -2.0 -0.05 .print dc I1(mn) .end Using HSPICE and TSMC 0.18 um CMOS technology model with 1.8 V power supply, plot log IDS versus VGS while varying VDS for an NMOS device with L=200 nm, W=800 nm and a PMOS with L=200 nm, W= 2 μm. Which device exhibits more DIBL(Drain-Induced Barrier Lowering)? Why do PMOS transistors typically have a higher VT than NMOS transistors? 解： linear scale logarithmic scale 图2 波形仿真 DIBL即是当沟道长度减小、电压VGS增加、使得漏结与源结的耗尽层靠近时，沟道中的电力线可以从漏区穿越到源区，并导致源极端势垒高度降低，从而源区注入到沟道的电子数量增加，结果漏极电流增加。沟道长度越短，DIBL效应就越严重。 由上图可以看出，与NMOS相比，PMOS不容易发生DIBL效应。这是因为PMOS的尺寸大约是NMOS的两倍，其P+区也相应增大（w大导致ad、as增大）从而具有较大的PN结，且其掺杂浓度较NMOS要大，因此