DesignspecificationofSDjukebox(draft).doc

CPLD DESIGN OF SD JUKE-BOX Version：　0.0.1 Date：　2004.09.22 Revision history Ver Date Revision Author Note Chapter Page Comments 0.0.1 2004/09/22 DRAFT ver. Li Peng Contents 1． Features 1 1.1 Relevant References 1 1.2 Device Parameters 1 1.3 Develop Environment 1 2． Top Overview 2 2.1 Top Block Diagram 2 2.2 I/O Port list of top level 2 2.3 Hierarchy of RTL Code 3 3． Command sets 4 4． Baud rate generation 5 5． Details of UART 6 5.1 Function Diagram 6 5.2 Receive FSM of UART 7 5.3 Transmit FSM of UART 9 6． Command verification and processing 12 6.1 Function Diagram of SEQ_CTRL 12 6.2 Command sequence check 13 6.3 Internal registers 15 6.3.1 Command regsiter 15 6.3.2 Slot number regsiter 15 6.3.3 Command status regsiter 15 6.3.4 Slot status regsiter 15 6.4 About request to send(RTS) 16 6.5 Answer to host 16 6.6 SD slot timing 19 6.7 External LED indication 19 6.8 Timing of Command processing 20 6.8.1 Normal case 20 6.8.2 Abnormal case 21 7． Pins Location 22 Figures Figure 21 Top Block Diagram 2 Figure 22 Hierarchy of code 3 Figure 41 Baud rate generation 5 Figure 51 Structure of UART 6 Figure 52 Receive state machine of UART 7 Figure 53 Transmit state machine of UART 9 Figure 61 Block Diagram of SEQ_CTRL 12 Figure 62 CMD_FSM 13 Figure 63 Timing of RTS 16 Figure 64 OP_FSM 16 Figure 65 SD slot connect timing 19 Figure 66 SD slot disconnect timing 19 Figure 67 Timing of Command C/S/W 20 Figure 68 Timing of Command D 20 Figure 69 Unknown command 21 Figure 610 Command received with parity or stop error 21 Tables Table 11 Main Device Parameters 1 Table 12 Develop Environment 1 Table 21 I/O Port list of top level 2 Table 31 SD slot commands 4 Table 51 I/O of UART 6 Table 61 I/O of SEQ_CTRL 12 Table 62 Command register 15 Table 63 Slot number register 15 Table 64 Command status register 15 Table 65 Slot status register 15 Table 71 Pins Location 22 Features A UART included. Up to 4 SD card slots support. Switching SD sl