硬盘结构及基本知识.pptVIP

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  • 2016-06-19 发布于江西
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硬盘结构及基本知识

Read-back Waveforms at Different User Densities UD = 0.75 UD= 1.5 UD = 2.0 Asynchronous Detection Peak Detection PLL Detector has NO knowledge of the bit timing PLL knows the bit timing No communication to Detector Synchronous Detection Peak Detection PLL Detector has knowledge of when a pulse may occur (bit timing) Can make a here / not-here decision Makes better decisions Signal to Noise Ratio (SNR) can be lower Sampled Detector allows for post compensation Model and remove ISI as an error source Synchronous Channel: Sampled Peak Detection 0.0 -0.2 -0.9 0.0 0.9 0.1

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