MSP单片机的时钟系统讲述.pptVIP

通过FLL锁频环电路自动校正使内部DCO振荡器稳定的运行在2.45MHz，相互关系式有：ACLK=XT1=32768Hz，MCLK=SMCLK=DCO=(74+1)*REFO=2457600Hz,这里XTICLK被选为ACLK，REFO是内部调整过的32768Hz参考时钟，提供一个稳定的参考时钟用作FLLREFCLK。 #include msp430f6638.h void main(void) { WDTCTL = WDTPW + WDTHOLD; P1DIR |= BIT0; // ACLK set out to pins P1SEL |= BIT0; P3DIR |= BIT4; // SMCLK set out to pins P3SEL |= BIT4; while(BAKCTL LOCKIO) // Unlock XT1 pins for operation BAKCTL = ~(LOCKIO); UCSCTL6 = ~(XT1OFF); // XT1 On UCSCTL6 |= XCAP_3; // Internal load cap // Loop until XT1 fault flag is cleared do { UCSCTL7 = ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 = ~OFIFG; // Clear fault flags }while (SFRIFG1OFIFG); // Test oscillator fault flag // Initialize DCO to 2.45MHz __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_3; // Set RSELx for DCO = 4.9 MHz UCSCTL2 = FLLD_1 + 74; // Set DCO Multiplier for 2.45MHz // (N + 1) * FLLRef = Fdco // (74 + 1) * 32768 = 2.45MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop // 32 x 32 x 2.45 MHz / 32,768 Hz = 76563 = MCLK cycles for DCO to settle __delay_cycles(76563); // Loop until XT1,XT2 DCO fault flag is cleared do { UCSCTL7 = ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 = ~OFIFG; // Clear fault flags }while (SFRIFG1OFIFG); // Test oscillator fault flag wh