华南理工大学2014年数字系统设计(全英)B卷答题.doc

《数字系统设计》试卷第  PAGE 14 页 共  NUMPAGES 14 页 Multiple choice test（2ⅹ5=10 marks） 1 . Which of the following statements on VHDL process is not true（ C ） A．a signal can be read in multiple processes; B. a signal can be assigned values for multiple times in a process, however, only the last assignment takes effect; C．a signal can be assigned values in different process; D．a process can be triggered either by means of sensitivity list or by wait statement; 2. Which of the following statements is not true（ D ） The working frequency of a synchronous digital system shouldn’t exceed the reciprocal (倒数) of its maximal delay; The working frequency of a synchronous digital system is limited by the delay of its components. Asynchronous digital system is more efficient in terms of resources than synchronous system. Asynchronous digital system is more reliable than synchronous system. 3. Which of the following statements on synthesis is not true（ D ） A. Synthesis is a transformation process from one representation of the design to another representation form； B. Synthesis transforms the high level HDL to low level hardware netlist, which is produced according to FPGA/CPLD structure； C. Synthesis is usually limited by the surface and speed of the circuit； D. Synthesis is a mapping process from high level description to low level hardware representation. The mapping relationship is unique and the synthesis result is unique. 4. Which of the following statements on VHDL simulationsynthesis is not true:（ B ） A. the time delay following the after statement can’t be synthesized; B. A pulse signal can’t propagate through the path if its duration is less than transport delay; C. For a VHDL signal, its initial value assigned in its declaration part is valid in simulation only; it’s ignored by the VHDL synthesis; D. Simulation is actually a process of checking and verification; 5. In state machine coding,（ A ）can save the resources for decoding and reduce the risk of illega