- 4
- 0
- 约小于1千字
- 约 15页
- 2016-07-25 发布于浙江
- 举报
Whole-Chip ESD Protection Strategy
for CMOS Integrated Circuits in Nanotechnology
Ming-Dou Ker and Hsin-Chin Jiang
2001 IEEE IEEE-NANO IEEE Conference on Nanotechnology;Structure;Abstract;Introduction;Introduction;ST Technique;ST Technique;ST Technique;ST Technique;ST Technique;ST Technique;ESD BUS;ESD BUS;Summary;Thanks
您可能关注的文档
- 《4A Isolated Half-Bridge Gate Driver with 4.5V to 18V Output Drive Voltage》.pptx
- 《A 2.5kV isolation 35kVus CMR 250Mbps 0.13mAMbps Digital Isolator in Standard CMOS with an on-chip small transformer》.ppt
- 《A 20MHz Switched-Current Sample-and-Hold Circuit for Current Mode Analog Iterative Decoders》.pptx
- 《A CMOS interdigital capacitive humidity sensor with polysilicon heaters》.pptx
- 《A Fully Integrated Linear CMOS Power Amplifier with High Output Power and Dynamic Range for WiMAX Application》.pptx
- 《A transient-enhanced NMOS low dropout voltage regulator with parallel feedback compensation》.pptx
- 《A Two-Stage Broadband Fully Integrated CMOS Linear Power Amplifier for LTE Applications》.pptx
- 《A UVLO Circuit in SiC Compatible With Power MOSFET Integration》.pptx
- 《Analysis of Feedback in Converter using Coreless Printed Circuit Board Transformer》.ppt
- 《Analysis of the coreless transformer in wireless battery vehicle charger》.ppt
原创力文档

文档评论(0)