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Subject : Analysis and Solution to Spurious Suppression of Direct
Digital Frequency Synthesis
Specialty : Micro and Solid Electronics
Name : Niu Chunquan (Signature)
Instructor : Liu Lianhui (Signature)
ABSTRACT
Frequency synthesizer is the key characters and equipment used in electronic systems.
The general frequency synthesis technologies are direct frequency synthesis, indirect
frequency synthesis and direct digital frequency synthesis. Direct digital synthesis is a method
of all-digital synthesis for generating signals of different frequencies. It has advantages of low
output phase noise, high frequency switching speed, high frequency resolution and can
produce arbitrary programmable waveforms. However, the output frequency and spurious
performance of DDS systems is not so much satisfactory by the influence of the deficiencies
of the structural.
The main work of this paper include some aspects as follows: An external PLL is
adopted to change the reference clock, then the output frequency is raised and the bandwidth
is expanded; Select carry adders and eight pipelines are used in the phase accumulator, then
the system operating speed is improved; D flip-flop structure is used in the phase accumulator,
then the spurious is reduced by changing the frequency control word; Waveform data is stored
in the ROM table with symmetrical data storing method, the interception of the phase
accumulator bits are indirectly reduced to achieve the purpose of reducing deviation.
During the experiment, taking considering its large chip integration and fast speed,
Altera FPGA chip EP2C5Q208C8 is selected to generate sinusoidal waveforms. This system
is implemented with Verilog HDL language on QuartusⅡ software. Simulation and
experimental results are verified the feasibility of the proposed method.
Key words: Di
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