电子设计自动化-多路波形发生器报告1.docxVIP

四、源程序及仿真波形library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity VHDL is port ( clk, reset:in std_logic; div:in std_logic_vector(1 downto 0); ctrl:in std_logic_vector(1 downto 0); outa,outb,outc:out std_logic);end VHDL; architecture abc of VHDL issignal count: std_logic_vector(7 downto 0); signal a:integer ;beginprocess(clk,reset)isbegina =conv_integer(div);if(clkevent and clk=1)then if(reset=0)then count else if count=6*a+5 then count else count=count+1; end if; end if;end if;end process; process(count) begin a =c