VHDL第六章.pptVIP

【例6-16】 ENTITY mul IS PORT (a, b, c, selx, sely : IN BIT; data_out : OUT BIT ); END mul; ARCHITECTURE ex OF mul IS SIGNAL temp : BIT; BEGIN p_a : PROCESS (a, b, selx) BEGIN IF (selx = 0) THEN temp = a; ELSE temp = b; END IF; END PROCESS p_a; p_b: PROCESS(temp, c, sely) BEGIN IF (sely = 0) THEN data_out = temp; ELSE data_out = c; END IF; END PROCESS p_b; END ex; 6.5 并行语句例解 【例6-17】 ARCHITECTURE dataflow OF mux IS SIGNAL seiect ： INTEGER RANGE 15 DOWNTO 0; BEGIN Select = 0 WHEN s0=’0’ AND s1=’0’ ELSE 1 WHEN s0=’1’ AND s1=’0’ ELSE 2 WHEN s0=’0’ AND s1=’1’ ELSE 3 ; x = a WHEN select=0 ELSE b WHEN select=1 ELSE c WHEN select=2 ELSE d ; . . . 6.2 双向电路和三态控制电路设计 6.2.1 三态门设计 【例】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY tri_s IS port ( enable : IN STD_LOGIC; datain : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END tri_s ; ARCHITECTURE bhv OF tri_s IS BEGIN PROCESS(enable,datain) BEGIN IF enable = 1 THEN dataout = datain ; ELSE dataout =ZZZZZZZZ ; END IF ; END PROCESS; END bhv; 6.2.2 双向端口设计 【例】 library ieee; use ieee.std_logic_1164.all; entity tri_state is port (control : in std_logic; in1: in std_logic_vector(7 downto 0); q : inout std_logic_vector(7 downto 0); x : out std_logic_vector(7 downto 0)); end tri_state; architecture body_tri of tri_state is begin process(control,q,in1) begin if (control = 0) then x = q ; else q = in1; x=ZZZZZZZZ ; end if; end process; end body_tri; 6.2.2 双向端口设计 例6-13的仿真波形图 6.2.2 双向端口设计 【例】 （以上部分同上例） process(control,q,in1) begin if (control=0) then x = q ; q = ZZZZZZZZ; else q = in1; x =ZZZZZZZZ； end if; end process; end body_tri; 例6-14的仿真波形图 6.2.2 双向端口设计 例6-13的综合结果 6.2.2 双向端口设计 图例6-14的综合结果 6.2.3 三态总线电路设计 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY tristate2 IS port ( input3, input2, input1, input0 :