毕业设计（论文）-基于FPGA的数据采集和回放系统的结构的设计.doc

PAGE PAGE 42 摘 要 数据采集系统一般由数据输入通道、数据存储与管理、数据处理、数据输出及显示这五个部分组成。输入通道要实现对被测对象的检测、采样和信号转换等工作。数据存储与管理要用存储器把采集到的数据存储起来，建立相应的数据库，并进行管理和调用。 本课题设计了以FPGA 为核心逻辑控制模块的高速数据采集和回放系统，设计中采用了自顶向下的方法,先从系统的角度分析该系统要完成哪些功能。用系统级行为描述表达一个包含输入输出的顶层模块，同时完成整个系统的模拟与性能分析。然后将系统划分为各个功能模块，详细论述了各模块的设计方法和控制流程。FPGA模块设计使用VHDL语言,在QUARTUSII中实现软件设计和完成仿真。最后在硬件上进行试验结果的验证，根据实验结果作修改后得出结果。本文给出了一些模块图形及端口说明和设计实现的思想,整个采集系统可实现现场模拟信号采集和信号的频率计数。 关键词：FPGA 数据采集 时钟逻辑运算 VHDL语言 Abstract Generally,data acquisition system is made of the data input channels,data storage and management,data processing,data output and display of these five parts.Input channels of the measured object in order to achieve the detection,sampling and signal conversion and so on .Data storage memory is used and managed to store data collected,which creats the corresponding database,and management and calls. The topic is designed to FPGA logic control module as the core of the high-speed data acquisition and playback system,which is used the method of top-down approach.In the first place,the perspective of system analysis of the system which functions to complete act with system-level descripition of the expression that contains the top-level input and output modules,at the same time the whole system simulation and performance analysis. Then the system is divided into various functional modules,which are use the language of VHDL in QUARTUSII to achieve the completion of the design and simulation software.Finally,it has test results for hardware verification,in accordance with the revised results for the outcome. In this paper, it has gave a number of modules and port descripition and graphic design ideas. The entire sampling system can be realized at the scene analog signal sampling and signal frequency count.[2 16 17] Key words：FPGA data acquisition clock logic count the language of VHDL 目 录 TOC \o 1-1 \h \z \u HYPERLINK \l _Toc229571055 摘要 PAGEREF _Toc229571055 \h I HYPERLINK \l _Toc229