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LIBRARY ieee; USE ieee.std_logic_1164.ALL; entity dff1 is port (d:in std_logic; clk:in std_logic; q:out std_logic); end ; architecture a of dff1 is begin process(clk) begin if(clkevent and clk=1)then q=d; end if; end process; end ; -------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY debouncing IS PORT( d_in, clk : IN STD_LOGIC; d_out: OUT STD_LOGIC ); END debouncing ; ARCHITECTURE a OF debouncing IS component dff1 is port (d:in std_logic; clk:in std_logic; q:out std_logic); end component ; signal q0, q1,q2,q3,q4 : std_logic ; BEGIN u1 : dff1 PORT MAP (d=d_in,q=q0,clk=clk); u2 : dff1 PORT MAP (d=q0,q=q1,clk=clk); u3 : dff1 PORT MAP (d=q1,q=q2,clk=clk); u4: dff1 PORT MAP (d=q2,q=q3,clk=clk); d_out=not(q0 and q1 and q2 and q3); END a; --------------------------------------------------------------------------------xiao dou library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fen_pin is port(clk3:IN std_logic; clkout1,clkout2:OUT std_logic); end fen_pin; architecture one of fen_pin is begin process(clk3) variable cnt:integer range 0 to variable tmp:std_logic; begin if(clk3event and clk3=1)then if cnt=3124999 then --125hz分频 cnt:=0; tmp:=not tmp; else cnt:=cnt+1; end if; end if; clkout1=tmp; end process; process(clk3) variable cnt:integer range 0 to 100000; variable tmp:std_logic; begin if(clk3event and clk3=1)then --32hz分频 if cnt=79999 then cnt:=0; tmp:=not tmp; else cnt:=cnt+1; end if; end if; clkout2=tmp; end process; end one; ---------------------------------------------------------------分频 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all ; use ieee.std_logic_unsigned.all ; library altera; use altera.maxplus2.all; --********************************************* entity elec_lock is port( clk_1:in std_logic; clk_scan : buffer std_logic_vector (3 downto 0) ; --scan sequence键盘扫描时序 key_in : in std_logic_vector (2 downto 0) ; --key in button c