偶数分频器VHDL的实现.docVIP

偶数分频器最易于实现，欲实现占空比为50%的偶数N分频，一般来说有两种方案：一是当计数器计数到N/2-1时，将输出电平进行一次翻转，同时给计数器一个复位信号，如此循环下去；二是当计数器输出为0到N/2-1时。时钟输出为0或1，计数器输出为N/2到N-1时，时钟输出为1或0，当计数器计数到N-1时，复位计数器，如此循环下去，第一种方案只能用于50%占空比，第二种方案可有限度的调占空比。library ieee ;use ieee.std_logic_1164.all ;use ieee.std_logic_arith.all ;use ieee.std_logic_unsigned.all; entity clk20 is port(clk_in : in std_logic; rst : in std_logic; clk_out: out std_logic); end entity clk20;architecture a of clk20 is signal clk_outQ:std_logic:=0; signal countQ: std_logic_vector(4 downto 0) :=00000; beginprocess(clk_in) begin if rst=1 then countQ=00000;elsif(clk_inevent and clk_in=1) then if (countQ9) then countQ=countQ+1;elseclk_outQ=not clk_outQ; countQ=(others=0); end if; end if; end process;clk_out=clk_outQ; end a;library ieee ;use ieee.std_logic_1164.all ;use ieee.std_logic_arith.all ;use ieee.std_logic_unsigned.all; entity clk6 is port(clk_in : in std_logic; rst : in std_logic; clk_out: out std_logic); end entity clk6;architecture b of clk6 issignal countQ: std_logic_vector(4 downto 0); begin process(clk_in) beginif rst=1 thencountQ=00000;elsif (clk_inevent and clk_in=1) then if(countQ19) then countQ=countQ+1;elsecountQ=(others=0); end if; end if;end process; process(countQ) begin if (countQ10) then clk_out=0; else clk_out=1; end if; end process;end b;