DLX指令系统.docVIP

DLX指令系统： add addfaddiadduadduiandandi bfpfbfptbnez cvtd2f cvtd2i cvtf2d cvtf2icvti2d cvti2f div divd divf divu eqd eqf ged gef gtd gtf j jal jalr jr lb lbu ld led lef lf lh lhi lhu ltd ltf lw movd movf movfp2i movi2fp movi2s movs2i mult multd multf multu ned nef nop or ori rfe sb sd seq seqi sf sge sgei sgt sgti sh sle slei sll slli slt slti sne snei sra srai srl srli sub subd subf subi subu subui sw trap xor xori  add 　　Ex: add r1,r2,r3　　R[regc] ← R[rega] + R[regb]　　All are signed integers.　　addd　　Ex: addd f4,f4,f6　　D[dregc] ← D[drega] + D[dregb]　　All are double precision floating point numbers. addf　　Ex: addf f3,f4,f5　　F[fregc] ← F[frega] + F[fregb]　　All are single precision floating point numbers. addi　　Ex: addi r5,r2,#5　　R[regb] ← R[rega] + imm16　　All are signed integers. addu　　Ex: addu r2,r3,r4　　R[regc] ← R[rega] + R[regb]　　All are unsigned integers. addui　　Ex: addui r2,r3,#28　　R[regb] ← R[rega] + uimm16　　All are unsigned integers. and　　Ex: and r2,r3,r4　　R[regc] ← R[rega] R[regb]　　All are unsigned integers. Logical and is performed on a bitwise basis. andi　　Ex: andi r3,r4,#5　　R[regb] ← R[rega] uimm16　　All are unsigned integers. Logical and is performed on a bitwise basis.beqz　　Ex: beqz r1,label　　if (R[rega] == 0) PC ← PC + imm16 + 4bfpf　　Ex: bfpf label　　if (fps == 0) PC ← PC + imm16 + 4　　fps is the floating point status bit. bfpt　　Ex: bfpt label　　if (fps == 1) PC ← PC + imm16 + 4　　fps is the floating point status bit. 　　bnez　　Ex: bnez r1,label　　if (R[rega] != 0) PC ← PC + imm16 + 4　　cvtd2f　　Ex: cvtd2f f1,f4　　F[fregc] ← (float) D[drega]　　Converts double precision floating point value to single precision floating point value. cvtd2i　　Ex: cvtd2i f1,f0　　F[fregc] ← (int) D[drega]　　Converts double precision floating point value to integer. cvtf2d　　Ex: cvtf2d f4,f9　　D[dregc] ← (double) F[frega]　　Converts single precision float to double. cvtf2i　　Ex: cvtf2i f3,f4　　F[fregc] ← (int)