基于Verilog HDL的时序电路设计word格式.docVIP

赣南师院 物理与电子信息学院 设计报告书 姓名： 班级： 学号： 指导老师： 陈 建 萍 时间： 目 录 摘要 ······················································································ 1 ·················································································· 1 1 引言···················································································· 2 2 时序逻辑电路······································································ 3 2.1 时序逻辑电路概述······························································ 3 2.2 同步时序逻辑电路的一般设计方法········································· 4 3 设计·············