AD转换寄存器表.docVIP

A/D转换寄存器表 /*** ATD0CTL1 - ATD 0 Control Register 1; 0x000002C1 ***/ union byte Byte; struct byte ETRIGCH0:1;External Trigger Channel Select Bit 0 */ byte ETRIGCH1:1;External Trigger Channel Select Bit 1 */ byte ETRIGCH2:1;External Trigger Channel Select Bit 2 */ byte ETRIGCH3:1;External Trigger Channel Select Bit 3 */ byte SMP_DIS:1;Discharge Before Sampling Bit */ byte SRES0:1;A/D转换精度选择Bit 0 */ byte SRES1:1;A/D转换精度选择Bit 1 */ byte ETRIGSEL:1;External Trigger Source Select */ Bits; /*** ATD0CTL2 - ATD 0 Control Register 2; 0x000002C2 ***/ union byte Byte; struct byte ACMPIE:1;ATD Compare Interrupt Enable */ byte ASCIE:1;ATD Sequence Complete Interrupt Enable */ byte ETRIGE:1;External Trigger Mode enable */ byte ETRIGP:1;External Trigger Polarity */ byte ETRIGLE:1;External Trigger Level/Edge control */ byte ICLKSTP:1;Internal Clock in Stop Mode Bit */ byte AFFC:1;ATD Fast Conversion Complete Flag Clear*/ byte:1; Bits; /*** ATD0CTL3 - ATD 0 Control Register 3; 0x000002C3 ***/ union byte Byte; struct byte FRZ0:1;Background Debug Freeze Enable Bit 0 */ byte FRZ1:1;Background Debug Freeze Enable Bit 1 */ byte FIFO:1;Result Register FIFO Mode */ byte S1C:1;Conversion Sequence Length 1 */ byte S2C:1;Conversion Sequence Length 2 */ byte S4C:1;Conversion Sequence Length 4 */ byte S8C:1;Conversion Sequence Length 8 */ byte DJM:1;Result Register Data Justification */ Bits; /*** ATD0CTL4 - ATD 0 Control Register 4; 0x000002C4 ***/ union byte Byte; struct byte PRS0:1;ATD Clock Prescaler 0 */ byte PRS1:1;ATD Clock Prescaler 1 */ byte PRS2:1;ATD Clock Prescaler 2 */ byte PRS3:1;ATD Clock Prescaler 3 */ byte PRS4:1;ATD Clock Prescaler 4 */ byte SMP0:1;Sample Time Select 0 */ byte SMP1:1;Sample Time Select 1 */ byte SMP2:1;Sample Time Select 2 */ Bits; ATD时钟的计算公式如下： ATDclock BusClock/Prescaler/2 /*** ATD0CTL5 - ATD 0 Control Register 5; 0x000002C5 ***/ union