a-dconversion.ppt

Dual Slope A-D conversion integrating A-D converter: no need for sample and hold found in digital multimeters utilizes current-voltage relationship of capacitor: Capacitor in feedback path of op amp Dual Slope Circuit: Dual Slope Timing: May need sign-changing op amp to match with circuit diagram Longer count time→greater number to be displayed at zero-crossing No need for sample and hold because signal is “averaged” over conversion time For DMM conversion cycle time is about 250 msec Bipolar analog representation:2’s complement code 1 -1 = 0 0 0 1  + 1 1 1 1 0 0 0 Review Fastest A-D conversion is flash with comparators D-A conversion with neg gain summation ampand R-2R ladder of resistors Successive approx for N bits of resolution needs N clock cycles for conversion; final clock cycle is end-of-conversion signal May need anti-aliasing LP filter and sample hold on input to A-D converter Dual slope A-D averages analog-in over long cycle Analog-to-digital conversion It’s what happens when a voltage signal is sent into a computer 6024E card: successive approx method Resolution: number of digital bits (12) Range: of voltage input (±10.24) Step size in mV: Range / 2^Res ≈ 5mV Sample rate (up to 200KHz) Start-of-conversion control Busy signal while conversion in progress Sample-and-hold Anti-aliasing LP filter Flash converter Dual-Slope A-D conversion where and what is the maximum error? ADC methods Flash converter: use of analog comparators Errors in ADC… (time-out for DAC details): Power-of-2 source resistors vs R-2R ladder analog switches for digital inputs reference voltage for HI; gnd for LO multiplying DAC Bipolar DAC ADA lab: 7524 + 353 Counting converter—variable sample rate Successive approximation Dual slope Analog comparator as 1-bit ADC X Y Z Ain 0 0 0 Ain ?*Vref 0 0 1 ?Ain? 0 1 1 ?Ain? 1 1 1 Ain ? TRUTH TABLE for converting X Y Z to binary numbers X Y Z B A 0 0 0 0 0 0 0 1 0 1 0 1 1 1