lec08-verilog-introduction-to-synthesis.ppt.pptVIP

DSD Objectives Learn What is synthesis Understand and appreciate differences between simulation and synthesis Various synthesis tools Get ready for the course laboratory and learn its limitations 2010 DSD * Logic Synthesis? Why? Assembly coding vs. C/Java programming Gate-level modeling vs. behavioral modeling 2010 DSD * Logic Design Course Standard products Adders 2010 DSD * Traditional Logic Design Flow 2010 DSD * Logic Synthesis Flow 2010 DSD * Logic Synthesis Process of generating detailed logic gates from higher-level description RTL (Register Transfer Level) / Logic Synthesis Behavi