Development of Bondgraph Models for Power Electronic Systems.ppt

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2016-10-07 发布于重庆
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Development of Bondgraph Models for Power Electronic Systems.ppt

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Development of Bondgraph Models for Power Electronic Systems

Multilevel inverters Topologies Inverter topologies cascading two level inverters Inverter topologies with open-end IM drive Inverter topologies with asymmetric DC link voltages Multilevel inverter topologies for common mode voltage elimination Two-level inverter scheme with common mode voltage elimination Higher level of multilevel inverter scheme DC-link capacitor voltage balancing winding induction motor drive Three-level structure with single power supply PWM signal generation for multilevel inverter A Space Phasor Based Self Adaptive Current Hysteresis Controller Multi-phase (six-phase) and multi motor drive Sensorless control scheme for IM drive 12-sided polygonal voltage space phasor generation. PWM inverters generate high frequency, high amplitude common mode voltages, which induces ‘shaft voltage’ on the rotor side When the induced shaft voltage exceeds the breakdown voltage of the lubricant in the bearings, result in large bearing currents Problems associated: erosion of the bearing material, premature mechanical failure of bearings leading to motor failure, increase in total leakage current through the ground conductor resulting into increased conducted EMI and false tripping of relays PWM inverters which do not generate common mode voltage are suggested as a solution to the above problems A three – level inverter scheme based on open-end winding configuration is proposed, which, uses only half the DC link voltage, compared to the scheme based on conventional NPC inverter The proposed scheme generates the three-level voltage waveforms across the motor phases with Zero common mode voltage in the motor phase voltage Zero common mode voltage in the pole voltage Balancing of the DC Link capacitor voltages after the controller is disabled for small interval, inner layer operation VC1 VC2 Balancing of the DC Link capacitor voltages after the controller is disabled for small interval, outer layer operation VC1 VC2 The DC link voltages and machine phase current